1. Field of the Invention
The present invention relates to a chip package and an electrical connection structure between a chip and a substrate. More particularly, the present invention relates to a high performance chip package and electrical connection structure between a chip and a substrate.
2. Description of the Related Art
FIG. 1A is a schematic cross-sectional view of a conventional chip package with a chip electrically connected to a lead frame using a wire-bonding process. FIG. 1B is a perspective view of the electrical connection structure between a chip and a substrate shown in FIG. 1A. As shown in FIGS. 1A and 1B, chip package 100 comprises chip 110, lead frame 120, signal wire 130a, ground wires 130b and insulation material 150. Lead frame 120 has die pad 122 and a plurality of identical leads 124.
To enhance the electrical characteristic between chip 110 and substrate 190, ground bonding pad 135 surrounding signal bonding pad 133 is being arranged on chip 110. Thus, a high-frequency signal is being transmitted from signal bonding pad 133 to lead 124a using a signal wire and finally being fed into substrate 190 through pad 192, in addition, ground signals are being outputted from ground bonding pad 135 in parallel, and further being respectively transmitted to lead 124b using ground wires, and finally respectively being shorted to ground through pad 194. In this regard, the grounding path of the high-frequency signal can be shorten by the neighboring grounding loop such that the signal distortion is reduced and consequently the electrical characteristic between chip 110 and substrate 190 is enhanced. Die pad 122 and lead 124b are electrically connected through pad 194 on substrate 190 to provide an electrical ground. Insulation material 150 encapsulates chip 110, lead frame 120, signal wire 130a and ground wires 130b. 
As shown in FIG. 1B, ground wires 130b are located at both sides of signal wire 130a to serve as an electrical shield. Ground wires 130b not only minimizes external electrical interference to signal wire 130a during signal transmission, but also prevents signal wire 130a from causing interference to other wires. Because signal wire 130a has a small cross-sectional area and a long length, relatively high impedance is produced during high frequency signal transmission. When the impedance of signal wire 130a deviates significantly from the system impedance, serious signal reflection occurs and the probability of producing computation errors in chip 110 increases considerably.
FIG. 2A is a schematic cross-sectional view of another conventional chip package with a chip electrically connected to a lead frame using a wire-bonding process. FIG. 2B is a perspective view of the electrical connection structure between a chip and a substrate shown in FIG. 2A. The chip package is almost identical to the one in FIGS. 1A and 1B except for the bonding of additional ground wires 140 linking chip 110 and die pad 122.
A conventional method used to improve the electrical characteristic of the aforementioned chip package 100 is to output high-frequency signals in parallel. Please refer to FIG. 3, which is a perspective view showing the double bonding-wire electrical connection structure between a chip and a substrate shown in FIGS. 1B and 2B. Instead of outputting a high-frequency signal of chip 110 through a single signal wire in FIGS. 1B and 2B, the high-frequency signals are being outputted in parallel using two signal wires in chip package 100, that is, signal bonding pad 133 of chip 110 is being connected to lead 124a of substrate 190 using two signal wires. As the result, the parasitic inductances induced respectively by the two parallel signal wires are parallel-connected, such that the capacitance and inductance between chip 110 and substrate 190 are better matched to have a better circuit performance.
However, to fabricate the foregoing improved chip package 100 of FIG. 3 is difficult in reality. For instance, both the surfaces of signal bonding pad 133 and lead 124a available for bonding are small such that the two signal wires connecting signal bonding pad 133 and lead 124a are very close to each other, and consequently reduces circuit performance thereof since not only the bonding is not easy to implement, but also the two signal wires are likely to contact with each other while applying a molding compound onto chip package 100.